Field of the Invention
The present invention relates to a memory system for a portable telephone and more particularly to a memory system for a portable telephone allowing storage of a large amount of data signals.
Description of the Background Art
FIG. 15 represents a schematic structure of a conventional portable telephone. In FIG. 15, the conventional portable telephone includes a high-frequency (radio-frequency) circuit 2 for transmitting/receiving a high-frequency signal via an antenna 1, a base band processing circuit 3 coupled to high-frequency circuit 2 and performing a process such as modulation at a basic frequency, a signal processing portion 4 coupled to base band processing circuit 3 and having a CODEC (coder/decoder) circuit 5 performing a processing of an audio signal such as encoding/decoding of a transmission/reception signal, a speaker 7 outputting a reproduced audio signal from, signal processing portion 4, and a microphone 6 for inputting an audio signal to be transmitted to signal processing portion 4.
High-frequency circuit 2 including an amplifier circuit amplifies a signal supplied from base band processing circuit 3 for transmission via antenna 1 upon transmission, and extracts a signal of a certain frequency range from a high-frequency signal supplied via antenna 1 upon reception.
Base band processing circuit 3 performs a process such as modulation at a basic frequency on an encoded transmission signal supplied from signal processing portion 4 and decodes (expands) a signal in a basic frequency range from a high-frequency signal supplied from high-frequency circuit 2.
Signal processing portion 4 includes encoding/decoding circuit (CODEC) 5 encoding/decoding a speech signal, and encodes an audio signal input from microphone 6 at the time of transmission, and decodes an audio signal supplied from base band processing circuit 3 for outputting via speaker 7 at the time of reception.
The conventional portable telephone further includes a key pad 10 coupled to an internal bus 9 for an input of necessary information, a control portion (MPU: microprocessor unit) 8 coupled to internal bus 9 for controlling operations of base band processing circuit 3, signal processing portion 4 and key pad 10, a linear flash memory 11 utilized as a read-only memory storing a program for controlling an operation of control portion 8, and a random access memory (RAM) 12 used as a working area for various processing by control portion 8.
Key pad 10 includes a ten-key and an on-hook key and is used for the input of necessary information.
Linear flash memory 11 is a non-volatile memory allowing random access. Now, the operation of the portable telephone shown in FIG. 15 will be described, with emphasis on a memory system related to the present invention.
A memory of the storage capacity of 8 to 32M bits (megabits) is used as linear flash memory 11 for storing user-specific data (such as a telephone directory) of a user of the portable telephone, accounting/connecting information or audio data (time-shift/message recording function) as well as an instruction code for control portion 8.
When the telephone enters a communication mode for performing transmission/reception through the manipulation of key pad 10, control portion 8 performs a control operation according to a program stored in linear flash memory 11, and then, signal processing portion 4 and base band processing circuit 3 each perform a predetermined processing operation under the control of control portion 8, and the transmission/reception of an audio signal (speech sound communication) is performed.
In operation, control portion 8 performs various processes according to the instruction codes stored in linear flash memory 11. Linear flash memory 11 can be accessed in a random manner and relatively fast. With instruction codes (process program) required by control portion 8 stored in linear flash memory 11, control portion 8 can perform a designated process at high-speed. In addition, linear flash memory 11 is a non-volatile memory and capable of storing a program required by control portion 8, user-specific rewritable information and so on as a read-only memory (ROM).
Random access memory (RAM) 12 is a high-speed memory and performs high-speed data transmission and temporary data saving in conjunction with control portion 8 upon processing by control portion 8.
Linear flash memory 11 is operable with a single power supply voltage and a low power supply voltage and can be accessed in a random manner. The memory cell structures of linear flash memories include an NOR type cell and DINOR (divided bit line NOR) type cell.
FIG. 16 represents a schematic structure of an array portion of the linear flash memory. In FIG. 16, an array structure of the NOR type flash memory is shown as a representative example of the linear flash memory. In FIG. 16, memory cells MCs are arranged in a matrix. A word line WL (WL0-WLm) is arranged corresponding to each row of memory cells MCs. A bit line BL is arranged corresponding to each column of memory cells MCs. In FIG. 16, a bit line BL provided for memory cells MCs arranged in a column is shown representatively. Memory cell MC has a drain connected to bit line BL via a contact and a source connected to a source line SL.
Generally, in a flash memory, memory cell MC is constituted of one MOS transistor with a double gate structure having a control gate and a floating gate. As one memory cell MC is constituted of one transistor, cost per bit is low and high density integration is allowed. The NOR type flash memory shown in FIG. 16, however, has a structure where bit line BL formed of metal interconnection line is connected directly to the drain of the memory cell transistor via a contact, and one contact hole is required for each two memory cells for a connection of the memory cells and the bit lines, thus impeding the higher integration.
In a programming operation of the NOR type flash memory, a high voltage (about 10 volts) is applied to a word line (control gate) WL, source line SL is set to a ground voltage, a voltage of a few volt is applied to bit line BL, and a current flows through a channel region of the memory cell transistor. The channel current is accelerated by a high field at a drain and hot electrons are produced to be injected into a floating gate. By the electron injection into the floating gate, a threshold voltage of the memory cell transistor rises and the programming is effectuated. As the programming is performed by the injection of hot electron, supply of a current to the memory cell is required at the time of programming. In view of the saving of current consumption, programming is usually performed a byte at a time.
On the other hand, in the erasing operation, 0 V is applied to a word line (control gate) and about 10 V is applied to source line SL for cells in a block of a few K to 64 K byte. Bit line BL is set to an electrically floating state. In this state, a tunneling current flows from the floating gate to the source due to the Fowler-Nordheim tunneling phenomenon. Then, the electrons are pulled out from the floating gate and the threshold voltage of the memory cell transistor falls.
In the NOR type flash memory, though the programming can be achieved a byte at a time as described above, the erasing operation is performed on a unit of a block having a commonly provided source line SL, for example, a block with 64 K byte storage capacity. Thus, when certain written data is to be rewritten, the erasing must be performed on a block including the data. Therefore, valid data stored in the block including data to be erased must temporarily be saved in random access memory (RAM) 12. The block containing data to be saved has, for example, a storage capacity of 64 K byte, and a storage capacity of a memory used for temporary data saving must be large enough to allow its rewriting. In addition, temporary saving of valid, data in this portion requires a management of a valid data region, thereby increasing the complexity of memory management.
Further, the linear flash memory has a longer access time compared with the operating speed of control portion 8. The access time of the linear flash memory is, for example, 70 ns (nanosecond) to about 120 ns. When control portion 8 operates in a high-speed communication mode such as W-CDMA (Wide Band Code Division Multiple Access), an access to linear flash memory 11 (reading of the instruction code) takes a long time, and the high-speed processing is precluded.
In addition, when the linear flash memory is constituted of an NOR type flash memory, a contact to bit line BL must be provided for every two memory cells MCs and the degree of integration is limited. Thus, when the storage capacity is increased for storage of large amount of data required for the high-speed communication service, the chip area becomes relatively large, the cost increases and development of a smaller portable telephone is impeded.